In a multicore processor chip, the L2 cache may be organized as one private L2 cache per core or a single shared L2 cache. The private cache approach requires smaller caches than a shared cache, and thus has faster cache access time than its shared counterpart. However, the private cache approach requires cache coherence enforcement, and the aggregate L2 capacity may not be used efficiently due to the data duplication. The cache coherence enforcement overhead and data duplication can be eliminated by sharing the cache, but at the expense of higher access time.

As the authors point out, one reason for high shared-cache access time is the wire delay that is a function of the distance between the requesting core and the L2 cache bank or partition with the requested cache line. To reduce the shared-cache access time, they propose to partition the cache into shared and private. The shared partition will be placed in the center to minimize the distance from cores to the shared L2 partition. The private partitions are placed close to their corresponding cores. Initially, a fetched cache line is placed in the private partition associated with the requesting core; it may gradually migrate to the shared partition, depending on the frequency of access to the cache line. In the case of shared partition replacement, the migrating cache line is swapped with the shared cache line being replaced. As a result of this migration and replacement, a cache line may be in any of the private or shared partitions; this leads to the search mechanism proposed by the authors. The basic search algorithm is to search the private partition of the requesting core first, and then the shared partition, and to perform a sequential search of the other private partitions.

While the paper proposes a novel mechanism to solve an important problem, the simulation studies do not provide enough details on the simulation environment. In addition, a comparison of the multicore case with the private L2 cache case, as well as a small shared L2 with a larger private L1 cache, would have made the advantage of the proposed mechanism clearer and more convincing. The authors fail to address or show scalability of the proposed scheme.

Overall, the paper is well written and, for the most part, easy to follow.