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Reducing register pressure in SMT processors through L2-miss-driven early register release
Sharkey J., Loew J., Ponomarev D. ACM Transactions on Architecture and Code Optimization5 (3):1-28,2008.Type:Article
Date Reviewed: Feb 27 2009

Superscalar processors and register renaming make it easy to simulate multiple processors on a single physical processor, improving the utilization of the computing units. When a memory reference to a location that is not in any cache occurs--a miss in the L2 cache--the instructions following the memory operation are dispatched; those that are not dependent on the delayed memory instruction are executed, but not completed, until the delayed memory operation completes. Therefore, this thread uses many of the registers in the register file, hindering the execution of other threads. This paper offers a mechanism for releasing registers to other threads.

The mechanism is activated when a memory operation misses in the L2 cache. It repeats scan instructions following the delayed instruction, identifying instructions that complete early. It stores the results of these instructions in memory space available in the instruction buffer, and frees the registers for use by other threads. When the value is needed, it is loaded from the instruction buffer rather than the physical register file.

The paper summarizes the effects of several variants of this mechanism, and compares it with other mechanisms using the M-Sim simulator and workloads derived from SPEC 2000. In some situations, the mechanism provides a 33 percent improvement in throughput, compared to other proposed mechanisms. Sharkey et al. indicate that this technique can be combined with other mechanisms.

The paper is readable, has an excellent bibliography, and is worth studying. The basis for this mechanism has been described in earlier papers. Most of this paper describes the comparison methodology and the competitive mechanisms.

Reviewer:  Charles Morgan Review #: CR136538 (0910-0926)
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Design Studies (C.4 ... )
 
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