This paper addresses the problem of reducing the time spent on testing core-to-core interconnections, namely on the verification of signal-integrity faults, typically relevant in high-performance systems on chip (SOC). The review of the state of the art is quite extensive and provides a good background for those interested in knowing what problems have been addressed and what solutions have been developed. At this point, the reader may also find interesting some material from a series of workshops targeting the same central theme--the IEEE International Workshops on Testing Embedded Core-based System-Chips (TECS), held from 1997 through 2002 [1]--although the paper fails to include a single reference to these workshops.

Most of the material cited by the authors comes from the testing community. I must again point out that some other works might also present some cross-fertilization ideas, especially those from the circuit simulation and modeling community.

Comparing the information provided by real tests with that resulting from simulation may lead to a better understanding of circuit parameters and help clarify the defect coverage of the test pattern set used for detecting signal-integrity faults on core-external interconnections--that is, all defects that potentially cause time-related faults are detected and characterized.