Synthesis flow involves translating a given design into an unbound logic network, followed by a technology mapping phase that targets different technologies and implementation styles. In the case of field programmable gate arrays (FPGAs), this involves grouping various elements of the logic network into look-up tables (LUTs) and other structures like programmable logic blocks (PLBs).

There are established algorithms for FPGA technology mapping targeting K-input LUTs that make use of feasible cuts at the nodes of the logic network to heuristically select good candidate cuts. Recent advances have demonstrated the efficiency and effectiveness of maintaining about four to eight priority cuts at the nodes instead of enumerating all the cuts.

In an earlier work [1], the same authors showed that the priority cut-based method needed modification when mapping to PLBs, since not all of the enumerated cut functions can be represented. The cutset of the subject graph was divided into subsets, one for cuts with up to four inputs and another for cuts with five to eight inputs. The priority cut ranking was then separately applied to both subsets. The method was referred to as staging the priority cuts. For filtering cuts that are mappable to a PLB, they proposed offline generation of library cells using an encoding to represent equivalent classes of functions.

In this work, Kennings et al. have extended their earlier work [1] with a detailed analysis of the logic coverage by Actel AX PLBs. Though some material appears common, the current paper addresses an area recovery strategy and timing-driven buffer insertion.

The presentation style is pleasant and provides sufficient background information. Details on the AX cell given in section 3 are very useful and educational. As in [1], sections 4, 5 and 6 describe the staged priority cuts, library generation, and filtering of cuts for the technology mapping targeting PLBs.

Section 7 shows that the heuristic area minimization done during technology mapping can be improved further by additional passes. Section 8 offers new contributions to the problem of buffer insertion after technology mapping. Heuristics based on measuring the impact on net delays are used to decide when to insert such buffers.

Section 9 presents detailed experimental results. Though the authors are attempting a general technology mapping solution, the AX cell seems to be MUX based; therefore, further experimentation is needed to check if a methodology based on bucket-brigade devices could have given better results for this specific situation. Overall, the paper is very impressive. Combined with [1], the contributions here are significant.