Tan et al. discuss the origin of Verilog, as well as its standardization and widespread adoption as one of the most popular hardware description languages (HDLs) for synthesis and behavioral modeling. The paper is well written and easy to understand. The authors have done a great job covering topics such as HDL simulation, and the use of field-programmable gate arrays (FPGAs) in prototyping and emulation.

I thought comparing and contrasting Verilog and VHDL would have given a nice edge to the paper. Although the paper is about Verilog HDL simulator technology, most of the simulation techniques described here remain the same regardless of the choice of the HDL: Verilog or VHDL.

The authors should also have mentioned some of the recent verification methodologies such as open verification methodology (OVM) and universal verification methodology (UVM), and some of the more recent verification technologies/tools such as Cadence Specman Elite.