The authors of this paper introduce some verification issues regarding systems on chip (SoC) structures and transfer protocols, and further introduce some of the means available to achieve network on chip (NoC) design correctness and automate verification, involving in vitro diagnostics (IVD), interactive whiteboard (IWB), and root cause analysis (RCA) tools and methods. The main contributions in this paper are the IVD that can flexibly interconnect verification intellectual properties (VIPs) and support coverage collection and the IWB to allow automation and creation of needed environments.

Usually, “60-70 percent of the entire product cycle for a complex logic chip is dedicated to verification tasks. Verification of complex functions that we can build using new design tools poses a challenge to reducing the total product time.” Traditional verification methods include constraint random verification (CRV), coverage-driven verification (CDV), assertion-based timing check (ABV), and even verification methodologies, such as open verification methodology (OVM), verification methodology manual (VMM), and universal verification methodology (UVM). Based on these main elements, IVD has been created to cope with VIP interconnection, and test configurations. It can predict correct accesses, discard transactions based on their attributes, and split transfers and responses by self-learning capabilities.

Furthermore, verification environment generation is another open question for verification engineers. Since the NoC architecture and Internet protocol (IP) integration are derived from industrial specifications, test bench generation is possible by creating computer-aided design (CAD) tools, such as IWB, presented in this paper. It allows users to generate complex environments very quickly, with hundreds of ports, with different protocols for different sizes.

In order to find out the IP/VIP interconnect bugs quickly, RCA has been used to filter logs, quick-check source code, and review signals and task execution in tables and waveforms.

All of the tools presented in this paper focus on the latest verification technologies and methodologies. The proposed tools and methods are new and industry-leading. However, without giving detailed information, the implementations and case studies are difficult to read.