Next-generation sequencing (NGS) is a big data problem. On the one hand, it is embarrassingly parallel; on the other hand, the memory accesses are irregular (noncontiguous). This is a unique application category where throwing extra cores and memory either together or in isolation does not help much. In fact, the paper shows that there is a tip-off point after which more cores make the problem worse. This paper describes the mapping of an NGS application on a field-programmable gate array (FPGA)-based platform.

The authors use the Convey HC-1ex platform, which has four Virtex6 LX760 FPGAs, coherently attached via the front-side bus (FSB) to a two-socket dual-core Xeon processor. The FPGA co-processor platform is connected to eight dual in-line memory modules (DIMMs) via eight customizable memory controllers. Each FPGA is connected to each memory controller, and the memory controller has scatter-gather capability. This implementation is compared against a multithreaded software-only implementation running on eight Intel Xeon eight-core processors with 1 TB memory.

The paper shows, yet again, that the FPGAs are well positioned to exploit the fine-grain parallelism in the application. On this particular FPGA platform, the custom memory controller with scatter-gather capability significantly helps with irregular memory accesses. Although the FPGA platform showed a performance gain of little more than two times over a 64-core system, the power efficiency gain was 28 times. The paper doesn’t have data regarding the cost of the systems, but that would be an interesting comparison point, too.

This paper presents compelling evidence of performance/watt gain for an important big data application as a motivation for the inclusion of FPGAs in data centers.