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Area-energy tradeoffs of logic wear-leveling for BTI-induced aging
Ashraf R., Khoshavi N., Alzahrani A., DeMara R., Kiamehr S., Tahoori M.  CF 2016 (Proceedings of the ACM International Conference on Computing Frontiers, Como, Italy, May 16-19, 2016)37-44.2016.Type:Proceedings
Date Reviewed: Oct 4 2016

As technology nodes are scaled down into the nanometer level, the reliability of the devices for an electronic chip becomes critical. Among various reliability threats, aging is one of the most prominent, as it introduces gradual parameter and metric (like performance) degradation, and eventually failures. Bias temperature instability (BTI) is a dominant aging issue that shifts the threshold voltage of the transistors when under voltage stress; when the voltage is removed, there is a slow recovery process. The longer the recovery process, the less cumulative aging will be. Various previous solutions aim to tune certain metrics to deal with aging, such as balancing the signal probability or adding guardband. But none of the solutions are perfect; additional overhead will still be introduced. One such tradeoff is usually energy and aging; by fixing aging issues, more energy needs to be consumed.

In this paper, Ashraf et al. propose a novel idea of dealing with aging at the circuit level by replicating the critical paths or near-critical paths. By taking advantage of such redundancy and switching between the replicated paths, the overall aging can be leveraged, thus the guardband can be reduced. Although the proposed solution will affect the area overhead, the paper presents a detailed evaluation and shows the area overhead is minimal if only replicating several critical path candidates. A design flow that can be adapted to the existing electronic design automation (EDA) tools is also proposed. The reported experimental results show that the guardband is significantly reduced; this is translated directly to the energy savings (about 31.98 percent). The paper also considers the area and energy tradeoff, and the conclusion is that the approach achieves very low area overhead while getting huge energy savings.

This paper shows a circuit-level implementation of coping with reliability by utilizing redundancy. It presents a very comprehensive analysis of various tradeoffs. While further study can be done, such as fanout, leakage issues and the added design efforts are some aspects that can still be addressed. Also, if dark silicon can be used together with the proposed circuit solution, there will be more improvements.

Reviewer:  Xinfei Guo Review #: CR144803 (1701-0048)
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