Verification is one of the most important parts of the whole chip design flow. Typically, verification claims more than 60 percent of the chip design schedule with functional level verification, pre-simulation, and post-simulation. In the front-end procedure, there are many verification methods today, like constrained-random test cases, assertion-based verification, and coverage-driven verification. Additionally, two dominant verification methodologies, universal verification methodology (UVM) and verification methodology manual (VMM), are very commonly used in industry.

In this paper, the authors propose a new method for generating cyclic-random sequences for post-silicon validation, which is similar to the front-end constrained-random technique supported by SystemVerilog. More specifically, the proposed work can eliminate some repeated test vectors by using a cube generation and scheduling algorithm, so that the simulation latency can be reduced. Since the post-simulation speed is very slow compared with front-end simulation, which is one reason for the usage only in functional verification, this new method is very useful to post-silicon simulation. In the experimental results, performance and resource costs are further evaluated and demonstrated.