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Melia: a MapReduce framework on OpenCL-based FPGAs
Wang Z., Zhang S., He B., Zhang W. IEEE Transactions on Parallel and Distributed Systems27 (12):3547-3560,2016.Type:Article
Date Reviewed: May 24 2017

Many web applications such as search engines and recommendation systems require operations on large datasets. The nature of computation in such applications is complex, which necessitates distributed operations on clusters of general-purpose processors using the MapReduce framework. As the amount of data grows, one of the main challenges facing system designers is building hardware systems that reduce the computation time without increasing the overall hardware cost and energy consumption. This paper describes a hardware implementation of MapReduce computation on field programmable gate arrays (FPGAs). Unlike previous approaches [1] that describe the computation using complex hardware description languages (HDLs), this paper uses a high-level programming language (OpenCL) and an automated compiler flow to implement map and reduce functions. I recommend this work as an excellent experimental case study that demonstrates (1) the benefits of using the OpenCL language for implementing computing functions on FPGAs and (2) the impact of OpenCL optimizations on application throughput. An experimental evaluation of seven commonly used MapReduce benchmarks using OpenCL on an Altera Stratix V FPGA is available in section 4.

What readers will find most interesting about this work is the OpenCL implementation of map and reduce functions (section 3). OpenCL makes it easier for software developers to implement, adapt, and optimize operations on FPGAs using familiar languages like C and C++. Map and reduce functions are translated to computation units in the FPGA using an automated compiler flow. The study further evaluates the performance and area tradeoffs of four OpenCL compiler optimizations: (1) memory coalescing, (2) kernel pipeline replication, (3) loop unrolling, and (4) local memory caching on application performance (section 4). It must be noted that these optimizations are not particularly novel because they are already included in the Altera OpenCL compiler. Rather, what is interesting here is an experimental evaluation of each individual optimization on the application throughput and FPGA resource usage. Another interesting contribution is a back-of-the-envelope cost model that predicts the optimal setting of OpenCL parameters to maximize application throughput. Readers will gain valuable insights on the impact of OpenCL optimizations on popular MapReduce benchmarks in single FPGA and multi-FPGA configurations. Section 4 compares the energy efficiency of MapReduce implementation on FPGAs, central processing units (CPUs), and graphics processing units (GPUs).

Overall, this is a very well-written research paper. The study will certainly be of interest to researchers who would like to evaluate MapReduce on heterogeneous hardware platforms. More generally, researchers and practitioners who would like to optimize applications on FPGAs using the OpenCL programming language will find this paper useful.

Reviewer:  Deepak Unnikrishnan Review #: CR145294 (1708-0537)
1) Shan, Y.; Wang, B.; Yan, J.; Wang, Y.; Xu, N.; Yang, H. FPMR: MapReduce framework on FPGA. In Proc. of FPGA '10. ACM, 2010, 93–102. http://dl.acm.org/citation.cfm?id=1723129
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  Reviewer Selected
Editor Recommended
 
 
Gate Arrays (B.7.1 ... )
 
 
Distributed Architectures (C.1.4 ... )
 
 
Graphics Processors (I.3.1 ... )
 
 
Optimization (G.1.6 )
 
 
Parallel Architectures (C.1.4 )
 
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