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Advances in computers: creativity in computing and dataflow supercomputing (vol. 104)
Hurson A., Milutinovic V., Academic Press, Cambridge, MA, 2017. 238 pp. Type: Book (978-0-128119-55-6)
Date Reviewed: Jan 25 2018

Computers and software applications are rapidly overwhelming our day-to-day lives. Computing has seen a rapid rise in the past four decades due to Moore’s law and the doubling of computing speeds in one-and-a-half to two years. However, Moore’s law is now slowing down due to several physical and logical barriers posed by clocking limitations, heating, and processor-memory segregation (known as the memory wall).

Parallel computing is the only way out if Moore’s law is to continue. However, parallel computing is difficult as it is not readily applicable to an existing sequential application. In the past, programs received the benefit of hardware accelerations without any further involvement, but this cannot happen in the case of parallelization.

This volume, in the “Advances in Computers” series, touches on the advances in dataflow computing based on practical research. Chapter 1 provides a very generic methodology for early researchers about how a new solution can be devised using a past knowledge base from diverse domains. It would be vital for early career researchers to go through this chapter and learn all of the various ways to solve/enhance the solution for a particular problem. They could then methodically categorize published research into different areas, and try different solutions using the outlined approaches.

Chapter 2 explores a Teraflux simulation framework for simulating 1012 transistor (1 tera) based single-chip 3D stacked processor-memory architecture (it is mentioned that this will be achieved in 2020, but it seems highly unlikely). It discusses existing options to simulate a gigantic 1000-core compute instance. This research nicely summarizes the simulation and emulation choices with a comparative feature matrix. Finally, the authors opted for the COTson parallel simulator to build the Teraflux simulation platform. The Teraflux experiment achieves the 1024-core machine using 32 cores with each core running 32 nodes. Though the chapter aims to build a dataflow computing model, there is little mention of the dataflow aspect in this chapter. It is observed that a thread scheduling unit (TSU) can be used to achieve the dataflow needs over the Teraflux framework.

The dataflow-based parallelization aspect is more deeply explored in the next chapter. It provides a complete overview of dataflow computing and its need to achieve the desired parallel computing outcome. At the core, dataflow programming is totally different than control-flow programming. Most algorithms and solutions are written from a control-flow perspective and dataflow requirements are to be redeveloped by using some control-flow to dataflow transformation. Until now, this process has been laborious and has required human involvement. It is also the core reason why progress on dataflow computing has been so slow during the past three or so decades, even though it is clearly known that dataflow computing could be much more powerful than its control-flow counterparts. Chapter 3 uses Maxeler dataflow architecture and MaxelerJ compiler to solve the lattice Boltzman computational fluid dynamics problem. The power-performance advantage is clearly established, showing the need for more friendly dataflow tools in the future. The following chapter (4) further explores dataflow solutions from the geoscience domain--a representative domain for high-performance computing (HPC). This chapter uses field-programmable gate arrays (FPGAs) as the reconfigurable computing fabric for the implementation of dataflow computing.

Finally, chapter 5 presents a parallelization solution for parsing context-free grammars (CFGs). CFG parsers are critical for natural language processing, bioinformatics, and pattern recognition applications. The experiment is once again performed on a Maxeler dataflow engine (MPC-C500 system). The performance achieved is 18 to 76 times faster than the optimized sequential parser.

This is a good resource for HPC and parallel computing researchers and academics. The methodologies from chapter 1 would be useful for researchers from any domain. The subsequent chapters show the parallelization techniques using present-day hardware/software and simulation tools. All of the parallelization tasks require human involvement and identification of the bottlenecks for overall acceptance of parallel computing for any application. Until this automation is achieved, it seems that everyday parallel computing will be limited to task-level parallelization to be run on different cores.

Reviewer:  Mohammed Ziaur Rahman Review #: CR145806 (1804-0159)
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