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Network on chip architecture for multi-agent systems in FPGA
Gerlein E., Mcginnity T., Belatreche A., Coleman S. ACM Transactions on Reconfigurable Technology and Systems10 (4):1-22,2017.Type:Article
Date Reviewed: Apr 17 2018

Hardware agent architecture is based on event-driven reactive architecture. In this architecture, each agent has defined tasks and these tasks interact using events. Events can be used to pass data and control information. In this paper, a hierarchical star-topology-based network-on-chip architecture for a hardware multiagent system is proposed.

To enable interaction and communication between different agents, star topology, where a switch is responsible for broadcasting the received message, is used. A cluster is a collection of multiple nodes sharing a common central switch. A hierarchical star configuration is formed by connecting multiple clusters through a switch. Star topology combined with a broadcast mechanism offers advantages in terms of resources and latency, but may result in an increase in traffic.

The architecture of the router is described in detail. The router facilitates communication within a cluster as well as between different clusters; hence, its design and efficiency become important. The router consists of I/O buffers, a round-robin scheduler, and a mix-demux crossbar switch. Also, it provides both master and slave open core protocol (OCP) signals on the interface.

Design space exploration is performed, and the effect of parameters such as buffer depth, packet width, and number of routers on resource requirements, power consumption, latency, and throughput is evaluated. Further, it is briefly compared with mesh topology.

As the number of clusters increases, traffic congestion at routers also increases. Also, to handle the increased traffic and avoid the possibility of deadlock, buffer size must be increased. Also, if the number of agents in a cluster grows, the complexity of the scheduler and switch also grows. These factors may limit the operating frequency and raise questions about the usability of this architecture for large-scale applications, and should be addressed.

This noteworthy and interesting research paper is well organized, and covers the necessary background information, making it easy for readers to understand the subject matter.

Reviewer:  Krishna Nagar Review #: CR145979 (1806-0310)
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Parallel Architectures (C.1.4 )
 
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