Finding the optimal energy savings corresponding to different quality constraints is one of the most important driving forces in approximate design, particularly for complex system on chips (SoCs) with multiple Internet protocols (IPs) integrated on edge devices, or energy-limited devices. This book thus presents a novel design flow, including synthesis, formal verification, and design for testing (DFT) as approximation-aware tools and methodologies, and introduces some steps of accuracy evaluation, such as the error metrics of error rate, worst-case error, average-case error, and bit-flip error, to find the best energy reduction related to the error bounds.

Traditionally, approximate design is mainly based on algorithm-level and register transfer level (RTL) designs. Only when functions with approximate design are accepted at the algorithm level can the behavioral model be implemented with Verilog or VHDL. However, this book introduces some new ideas to involve approximate designs in integrated circuit (IC) design flow. Chapter 7 discusses a processor for high-performance on-demand approximate computing (ProACt) architecture as an example of on-demand approximation. As per the evaluation, ProACt power consumption (18.66 milliwatt/megahertz (mW/MHz)) is much lower than most other processors.

The difference between functional verification and formal verification should be clarified somewhere, for example, in Figure 1.1. Traditionally, formal verification focuses on checking the equivalence of RTL and synthesis netlists. But recent definitions of formal verification also cover all the static verification technologies compared to dynamic ways like simulation or functional verification, including universal verification methodology/verification methodology manual (UVM/VMM), coverage, assertion, and constrained random testing. In this book, formal verification is updated to check the functionality and quality bound with approximate designs.

Chapters 3 and 4 introduce a new definition of formal verification. The core idea is to check the functionality of the netlist within a quality bound, instead of statically checking the equivalence between RTL design and the synthesis netlist as in traditional formal verification.

The functionality of traditional synthesis tools like Design Compiler (DC) for ASIC design and Vivado for field-programmable gate array (FPGA) design is to convert or map RTL into specific gate-level netlists or slices of lookup tables, register, and so on. In order to optimize the area-time-energy by involving approximations of the design during synthesis, a new synthesis tool is needed, which is introduced in chapter 5.

I am now wondering how a large scale of the design can be implemented using the technologies introduced in chapters 3 through 5. As system-level design, the optimization in synthesis is very complicated. The timing issues would commonly occur in this step. So, how can one ensure the functionality and timing check after approximating the synthesis of the netlist? I am also curious about how to cover the test plans in the back-end design flow when approximating the design or the netlist, since the simulation in the back-end is too slow.

In conclusion, this book introduces many good ideas about IC design flow for approximate design. It has a great potential to optimize the traditional electronic design automation (EDA) tools to be approximation-aware software in the future. However, design automation in IC design flow is much more time-consuming compared with the algorithm design. The performance of involving error-tolerant synthesis and formal verification into large-scale designs needs to be further evaluated in terms of execution time, functionality guarantee, and timing constraints.

This book is suitable for researchers and engineers with experience and background in ASIC and FPGA design flow. The focus is on EDA tool development and chip design flow, not an introduction to approximate design on ICs and systems.