In-memory computing is one of the most important paradigm shifts in today’s processing models. This interesting and innovative approach is possible because not only do we have new ideas on how to perform data processing without the central processing unit (CPU), but also there are technological solutions that address such challenges. Obviously, if something new is proposed, we have to solve some previously unknown problems. In this particular case, persistent data for in-memory applications is a critical bottleneck.
This problem mostly relates to technological limitations, and byte-accessible non-volatile memory (NVM) can be an interesting solution. Besides the technological challenges, there are architectural solutions that “reduce the overall system complexity and overhead.” The authors propose “a high-frequency, whole-memory checkpointing technique.” The idea is not new, but “a key challenge is how to efficiently guarantee crash consistency of each checkpoint.” One possible solution is hardware redo/undo logging or copy-on-write (CoW) (“[which] require little metadata in the memory controller”); however, “redo/undo logging or copy-on-write (CoW) requires at least 2× NVM writes than the amount of actual dirty data.” NVM writes are “one order of magnitude slower than DRAM,” and the limited endurance of NVM is also notable (109 cycles).
Thus, the authors propose a new checkpointing scheme that needs “minimal extra NVM writes” and results in “minimal metadata space/management overhead” (only 3.7 percent NVM space wastage). They apply “dual-page checkpointing to a DRAM + NVM hybrid persistent memory system.” The configured memory controller is “transparent to applications”; there is no need to rewrite the code “for generating and restoring checkpoints.”
Details about this interesting solution can be found in Sections 3 and 4, which cover key implementations and optimizations. Section 5 tests performance.
In summary, the authors present “an architectural approach to supporting in-memory data persistence on NVM.” It is based on “a simple ... checkpointing mechanism [implemented] in the memory controller,” and solves the tradeoff dilemma between additional NVM data writes and extra metadata hardware. Results show that the presented solution “outperforms the state-of-the-art software solution by 13.6× higher throughput, and latest checkpointing techniques by 1.28×.”
