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A multi-level-optimization framework for FPGA-based cellular neural network implementation
Liu Z., Luo S., Xu X., Shi Y., Zhuo C. ACM Journal on Emerging Technologies in Computing Systems14 (4):1-17,2018.Type:Article
Date Reviewed: Dec 3 2019

Multi-level optimizations for cellular neural network design with Zybo and ZedBoard field-programmable gate arrays (FPGAs), including the system, module, and design levels, are presented in this paper. At the system level, parallel and tiling processing and data-reuse methodologies are used.

Module-level optimization is mainly based on converting floating-point operations to fixed-point operations. Instead of integrating the floating-point multiplier Internet protocols (IPs) directly, the authors use shifters and adders to reduce resource cost and power consumption. The optimization is not new, but hasn’t been applied for most of the existing works on neural networks. The floating-point to fixed-point conversion will eventually trade off accuracy for reduced design complexity, which is not discussed. More research on the quality-energy balance is needed. Additionally, I am wondering if the latest synthesis tools are still not able to optimize the design on a1xy1+a1xy2+a1xy3 as just one multiplier instead of three.

At the design space level, the authors use as few AXI-IPs as possible to meet the design specifications. It is obvious that the AXI interface or protocol itself is complicated, using more slices and power compared to some application-specific submodules like multipliers and adders.

Most of the ideas used on the FPGA design are not new, but the experiments and implementations are thorough and indeed show improvements in terms of energy efficiency and latency. The energy and speed improvements are a significant contribution to the design of hardware systems like cellular neural networks.

Reviewer:  Xiaokun Yang Review #: CR146803 (2002-0028)
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General (B.0 )
 
 
Integrated Circuits (B.7 )
 
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