Assume that a wafer contains an array of identical integrated circuits, that a test can be applied to all of these in parallel, and that the test results for each IC can be compared. In the usual case a test is applied and the results are analyzed by some external hardware. This paper proposes that the status of an IC be determined by voting (comparison of the test results) rather than by analysis of the results by external hardware.

The probabilities of optimistic (a faulty circuit declared good) and pessimistic (a good circuit declared faulty) results are computed. The fault coverage of the test is factored into this, but is not an issue for the method.

The paper covers the issues of wafer-scale testing quite well. One concern, that of communication between wafers, has been met since the submission of the paper by IEEE standard 1149.1 on boundary scan (see Jarwala and Zorian [1] for an application of boundary scan to wafer testing). One weakness of the paper is that I find it hard to imagine how test inputs can be applied to each circuit at speed. Perhaps if built-in self-test were used for stimulus generation and output data compression, wafer testing would be more practical. In summary, I found this an interesting exercise with limited short-term practical value.