The goal of the paper is to develop synthesis techniques for the next-state logic in finite state machines (FSMs) to optimize power, area, and delay. While technically sound, numerous grammatical, typographical, and figure errors cloud the presentation. The heuristic state minimization algorithm operates in O(n2) time, where n is the original number of states. The heuristic state assignment algorithm targets reduced power, area, and propagation delays for a specified cell library. No complexity analysis is provided for the state assignment algorithm.
Shiue compared implementations of the MCNC FSM benchmarks obtained using his techniques (labeled "with optimization") with other implementations of the same benchmarks (labeled "without optimization"). The author’s implementations were better with respect to delay, power, and area in all but one case. Since there was no mention of how the implementations labeled “without optimization” were obtained, other than “existing coding,” the meaning of the data is unclear. In any event, use of the term “optimization” is inappropriate since the author uses heuristic procedures to avoid the complexity needed to truly obtain optimal implementations.
In the introduction, the author mentions several different approaches described in previous publications that could be considered competitors to his proposed “optimal” solutions. In my opinion, it would have been of value to see comparisons of the best implementations of the MCNC FSMs found by his competitors with his implementations, rather than with the unspecified implementations labeled “without optimization.”
In summary, the techniques presented in this paper are very interesting, and should prove to be of value to both researchers and designers, even though the optimality claims are not justified, in my opinion.
