In this paper, Zhang, Jha, and Shang improve the NATURE architecture, which they previously proposed, and present a unified, dynamically reconfigurable architecture with enhanced area and power for data-dominated applications. The other contribution of this work is the placement of this architecture using three-dimensional (3D) technology. The authors also investigate implementing the design using FinFETs--a double-gate complementary metal-oxide semiconductor (CMOS) technology--and explain a back-gate biasing method to reduce power consumption.

The folding methodology introduced makes the system reconfigurable and improves power and area-delay product metrics by using coarse-grain digital signal processing (DSP) blocks. The authors introduce some details of 3D placement, but it is not obvious how much improvement in power and delay this provides. Later, they show that by using proper back-gate biasing, it is possible to decrease the power consumption of a gate by 150 times, at the expense of a two-times increase in delay. At the end, the results show that using the 3D technology along with FinFETs can achieve an up-to-eight-times power reduction and a 17-times area-delay product increase for wavelet and discrete cosine transform (DCT) applications.