This is a very good academic paper, but it contains little of practical value to most design teams. It shows that the area of local routing networks that connect cluster inputs to individual lookup table (LUT) inputs can be significantly reduced in field-programmable gate arrays (FPGAs)--when compared to fully connected networks--while maintaining the property that the cluster inputs are logically equivalent (that is, any input variable can be connected to any cluster input). Therefore, this paper will be of practical interest only to the few design groups that design FPGA architectures.

It will provide no useful guidance for the majority of design groups who use FPGAs to implement logic designs. Even for its limited audience, the results are of little value because it is based on the assumption that all inputs to a LUT can be made logically equivalent to all other inputs by reconfiguring the LUT. While this is true for simple LUTs, such as those in the “academic” FPGA used by the authors to generate area comparisons, it is not generally true for modern complex LUT devices. Therefore, before using the techniques in the paper, an FPGA designer will probably have to interpret the paper’s results for his or her own type of LUT. The final limitation is that area savings fall off quickly as the number of LUTs in a cluster increases and the number of inputs to an LUT increases. Since the industry trend is toward ever-larger FPGAs, the paper’s results will become less important in the future.