Power consumption is a critical performance parameter in integrated circuit design. Scaling down the operating supply voltage is a means to achieve this goal in ultra-low power circuits. The variability of process parameters has been increasing with the scaling down of transistor sizes. Therefore, accurately estimating the minimum supply voltage is very important for the reliable operation of low-power circuits in the presence of process variations.

In this research paper, the authors develop a closed-form expression for estimating the minimum operating voltage for complementary metal-oxide-semiconductor (CMOS) inverters. This expression takes the variability of switching the threshold voltage of transistors. Within-die variation and die-to-die variation in the threshold voltage are included in the expression. The expression is then extended to not AND (NAND) and not OR (NOR) gates. The proper operation of long logic gate chains that are based on the minimum operating voltage from the expression are verified through circuit simulations and in fabricated silicon circuits.

The paper’s major contribution is the accurate and quick estimation of minimum supply voltage, which eliminates the reliance on Monte Carlo simulations.