This paper examines the problem of optimizing the space requirements and latency for a field-programmable gate array (FPGA) implementation of a Sobel edge detection filter. Sobel edge detection applies horizontal and vertical convolutions to compute gradients in those respective directions, in order to highlight edges in an image.

The bulk of the paper focuses on deriving efficient expressions for the convolution. In particular, the authors consider the alternative, that is, a more expensive in terms of space representation of the image that allows easy access to the groups of pixels needed for input to the convolution filter. They also express the equation of the convolution and then work through it to arrive at a final form for implementation in digital logic. Some of these simplifications stem from the restriction to an 8-bit arithmetic. Although it is an interesting exercise, one is led to wonder whether a compiler for the FPGA target could automate much of this.

The paper also presents practical results in terms of gate count and timing limits from an actual implementation. They show how the hand-derived optimizations led to significant improvements over prior work. Overall, the paper is an interesting read and relatively easy to access, even for readers who are not well versed in digital logic.