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Patmos:a time-predictable microprocessor
Schoeberl M., Puffitsch W., Hepp S., Huber B., Prokesch D. Real-Time Systems54(2):389-423,2018.Type:Article |
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Date Reviewed: 09/18/18 |
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While general-purpose computing looks for a good average execution time, a vital parameter of real-time/embedded platforms (mission critical applications, like in avionics) is the worst-case execution time (WCET) [1]: the upper bounds of execution times. Such applications need a time-predictable execution platform [2]. This paper presents Patmos, a microprocessor designed for real-time/embedded systems [3]. The presentation level is suitable for both industry and academia. The paper presents Patmos as a four-target project: (1) “the design and implementation of a time-predictable processor,” (2) “a compiler supporting the processor,” (3) “a WCET analysis tool for [this processor],” and (4) performance evaluation. In addition, the paper presents the T-CREST project (a multicore platform using Patmos processors [4]) and discusses the related works of other research teams. The Patmos architecture is based on instruction pipelining [5], instruction predication [6], and memory hierarchy [7]. It is a statically scheduled 32-bit dual-issue reduced instruction set computer (RISC) processor. All instructions are fully predicated. Patmos uses three memory caches: one cache for instructions, operating on entire methods/functions (method cache [3]); one cache for stack allocated data; and one cache for the other data. The Patmos compiler, based on a low-level virtual machine (LLVM) infrastructure [3], has two tasks: (1) provide optimal code for this architecture (dual-issue support, single-path flow, or stack/method caches support) and (2) provide information for WCET analysis. The source code is translated into intermediate LLVM code, from which the executable and a metainfo file for timing analysis are generated in parallel. The authors did a battery of evaluation tests, and the results are synthesized in the paper.
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1) |
Wilhelm, R.; Engblom, J.; Emerdahl, A.; Holsti, N.; Thesing, S.; Whalley, D.; Bernat, G.; Ferdinand, C.; Heckmann, R.; Mitra, T.; Mueller, F.; Puaut, I.; Puschner, P.; Staschulat, J.; Stenström, P. The worst-case execution time problem—overview of methods and survey of tools. ACM Transactions on Embedded Computing Systems 7, 3 (2008), Article No. 36 .
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2) |
Manolache, S.; Eles, P.; Peng, Z. Schedulability analysis of applications with stochastic task execution times. ACM Transactions on Embedded Computing Systems 3, 4(2004), 706–735.
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3) |
Schoeberl, M.; Brandner, F.; Hepp, S.; Puffitsch, W.; Prokesch, D. Patmos reference handbook. Technical University of Denmark, Copenhagen, Denmark, 2014, http://patmos.compute.dtu.dk/patmos_handbook.pdf.
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4) |
Schoeberl, M.; Abbaspour, S.; Akesson, B.; Audsley, N.; Capasso, R.; Garside, J.; Goossens, K.; Goossens, S.; Hansen, S.; Heckmann, R.; Hepp, S.; Huber, B.; Jordan, A.; Kasapaki, E.; Knoop, J.; Li, Y.; Prokesch, D.; Puffitsch, W.; Puschner, P.; Rocha, A.; Silva, C.; Sparsø, J.; Tocchi, A. T-CREST: time-predictable multi-core architecture for embedded systems. Journal of Systems Architecture 61, 9 (2015), 449 – 471.
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5) |
Wilhelm, R.; Grund, D.; Reineke, J.; Schlickling, M.; Pister, M.; Ferdinand, C. Memory hierarchies, pipelines, and buses for future architectures in time-critical embedded systems. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 28, 7(2009), 966–978.
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6) |
Puschner, P.; Kirner, R.; Huber, B.; Prokesch, D. Compiling for time predictability. In: Computer safety, reliability, and security (LNCS 7613). 382-391, Springer, Berlin, Germany, 2012.
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7) |
Hennessy, J.; Patterson, D. A. Computer architecture: a quantitative approach (5th ed.). Morgan Kaufmann, Waltham, MA, 2012.
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Reviewer:
Pierre Radulescu-Banu
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Review #: CR146245 (1812-0639) |
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