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Arul, Joseph
Fu Jen Catholic University
Hsin Chuang City,Taipei Hsien, Taiwan
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Joseph M. Arul is currently an associate professor in the Department of Computer Science and Information Engineering at Fu Jen Catholic University. He received his master’s degree in computer science from DePaul University in 1994, and his PhD from the University of Alabama in Huntsville (UAH) in 2001.

Joseph’s main research areas include computer architecture, multithreaded systems, dataflow concepts, parallel programs, embedded systems, and cloud computing.

For more than 20 years, Joseph has contributed to Computing Reviews. Reviewing for CR has allowed him to broaden his knowledge in different areas. He is currently exploring how generative adversarial networks (GAN) contribute to image processing in artificial intelligence (AI).

Date Reviewed  
- 10 of 24 reviews

   Integrating serverless architecture: using Azure Functions, Cosmos DB, and SignalR Service
Vemula R., Apress, New York, NY, 2019. 456 pp.  Type: Book (978-1-484244-88-3)

Integrating serverless architecture covers how to build the Twitter bot application from scratch via a step-by-step method, including the basic installation software needed to achieve fundamental serverless computing. As the ter...

Aug 2 2021  
  Scratchpad-memory management for multi-threaded applications on many-core architectures
Venkataramani V., Chan M., Mitra T. ACM Transactions on Embedded Computing Systems 18(1): 1-28, 2019.  Type: Article

This paper focuses on improving many-core architectures via software programmable or scratchpad memory (SPM):...

Oct 7 2020  
   Formation control: approaches for distributed agents
Ahn H., Springer International Publishing, New York, NY, 2019. 360 pp.  Type: Book (978-3-030151-86-7)

The study of autonomous systems such as drones is an “emerging field in network science and engineering.” In the future, these systems need to cooperatively operate without collision, communicating with each other &...

Apr 16 2020  
  Introduction to logic circuits & logic design with Verilog
LaMeres B., Springer International Publishing, New York, NY, 2017. 459 pp.  Type: Book (978-3-319538-82-2)

This book begins with an introduction to the analog versus digital question, and then describes the advantages of today’s popular digital systems. Like any other digital system book, it starts with a description of the number...

Jul 23 2018  
  Optimizing the configuration of an heterogeneous architecture of sensors for activity recognition, using the extended belief rule-based inference methodology
Espinilla M., Medina J., Calzada A., Liu J., Martínez L., Nugent C. Microprocessors & Microsystems 52 381-390, 2017.  Type: Article

The aging populations in many countries are on the verge of increasing, and the incidence of common diseases related to this group, such as dementia, seem to by rising day by day. Hence, there is a growing need to have sensor-based act...

May 17 2018  
   Digital logic design using Verilog: coding and RTL synthesis
Taraate V., Springer International Publishing, New York, NY, 2016. 416 pp.  Type: Book (978-8-132227-89-2)

Anyone who wants to read this book must have a sound background in the theoretical aspects of digital logic design. This book presents digital logic design using the hardware description language known as Verilog. The book starts with ...

Apr 27 2017  
  Parallel programming model for the Epiphany many-core coprocessor using threaded MPI
Ross J., Richie D., Park S., Shires D. Microprocessors & Microsystems 43(C): 95-103, 2016.  Type: Article

This particular parallel programming model using threaded message passing interface (MPI) was implemented on a special architecture, the Adapteva Epiphany. The Epiphany IV architecture is comprised of 64 cores arranged in 2D tiled mesh...

Aug 29 2016  
  Modular vector processor architecture targeting at data-level parallelism
Rooholamin S., Ziavras S. Microprocessors & Microsystems 39(4): 237-249, 2015.  Type: Article

This research presents a VHSIC hardware description language (VHDL) vector processor architecture specifically designed to address data-level parallelism by separating the vector lanes to use its own private memory, avoiding any stalls...

Apr 8 2016  
  Selective switching mechanism in virtual machines via support vector machines and transfer learning
Kuang W., Brown L., Wang Z. Machine Learning 101(1-3): 137-161, 2015.  Type: Article

In current virtual machine design approaches, two schemes are popularly used by “modern virtual machine memory managers”: shadow paging (SP) and hardware-assisted paging (HAP). Since both schemes perform well, dynam...

Mar 23 2016  
  Customized pipeline and instruction set architecture for embedded processing engines
Yazdanbakhsh A., Salehi M., Fakhraie S. The Journal of Supercomputing 68(2): 948-977, 2014.  Type: Article

This research aims to improve performance in embedded application domains. The authors have not proposed an entirely new set of instructions, but rather have customized instructions by building a dataflow graph (DFG) and profiling the ...

Apr 9 2015  
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