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  Browse All Reviews > Hardware (B) > Performance And Reliability (B.8) > Performance Analysis And Design Aids (B.8.2)  
 
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  1-10 of 10 Reviews about "Performance Analysis And Design Aids (B.8.2)": Date Reviewed
  Methodology to verify, debug and evaluate performances of NoC based interconnects
Oury P., Heaton N., Penman S.  NoCArc 2015 (Proceedings of the 8th International Workshop on Network on Chip Architectures, Waikiki, HI, Dec 5, 2015) 39-42, 2015.  Type: Proceedings

The authors of this paper introduce some verification issues regarding systems on chip (SoC) structures and transfer protocols, and further introduce some of the means available to achieve network on chip (NoC) design correctness and a...

Feb 22 2016
  Characterization, monitoring and evaluation of operational performance trends on server processor hardware
Sithole E., McClean S., Scotney B., Parr G., Moore A., Bustard D., Dawson S., Bustard D.  ICPE 2011 (Proceeding of the 2nd Joint WOSP/SIPEW International Conference on Performance Engineering, Karlsruhe, Germany, Mar 14-16, 2011) 391-402, 2011.  Type: Proceedings

With the increase in data-intensive applications, enterprise information technology (IT) companies are focusing on the performance of processor hardware to determine the optimal central processing unit (CPU) and memory selection....

Dec 20 2011
  How green is green?
Want R. IEEE Pervasive Computing 8(1): 2-4, 2009.  Type: Article

Using pervasive computing, Want attempts to relate a variety of concerns about energy conservation and carbon dioxide (CO2) emissions....

Jul 7 2010
  A comparison of CPUs, GPUs, FPGAs, and massively parallel processor arrays for random number generation
Thomas D., Howes L., Luk W.  FPGA 2009 (Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Monterey, California, Feb 22-24, 2009) 63-72, 2009.  Type: Proceedings

As random number generators (RNGs) are widely used in Monte Carlo methods and signal processing, high-performance RNGs have been extensively researched, both as algorithms and hardware architectures. Hardware-wise, the performance and ...

May 1 2009
  Timing optimization in logic with interconnect
Morgenshtein A., Friedman E., Ginosar R., Kolodny A.  System level interconnect prediction (Proceedings of the Tenth International Workshop on System Level Interconnect Prediction, Newcastle, United Kingdom, Apr 5-8, 2008) 19-26, 2008.  Type: Proceedings

The general timing optimization problem can be defined as reducing the delay of a logic path propagating over a distance between two points, while performing a logical function. This paper discusses the timing optimization in logic pat...

Jun 11 2008
  Precise automatable analytical modeling of the cache behavior of codes with indirections
Andrade D., Fraguela B., Doallo R. ACM Transactions on Architecture and Code Optimization 4(3): 16-es, 2007.  Type: Article

The modeling of cache performance and the prediction of cache miss probability are difficult problems. Modeling the cache performance by trace-driven simulations has been widely studied in the past. However, the validity of these studi...

Nov 28 2007
  Systems architecture: the empirical way: abstract architectures to ‘optimal’ systems
Hellestrand G.  Embedded software (Proceedings of the 5th ACM International Conference on Embedded Software, Jersey City, NJ, USA, Sep 18-22, 2005) 147-158, 2005.  Type: Proceedings

The systems architecture of embedded software-electronics control systems (SECS) design is the focus of this paper. Since time-to-market requirements drive the development of products in this engineering area, there is no chance for co...

Nov 30 2005
  Circuit design with VHDL
Pedroni V., MIT Press, Cambridge, MA, 2004.  Type: Book (9780262162241)

Very-high-speed integrated circuit (VHSIC) hardware description language (VHDL) is one of the languages commonly used to model the behavior of digital systems. VHDL is used to simulate, as well as to synthesize, digital circuits. This ...

Dec 20 2004
  Understanding Why Correlation Profiling Improves the Predictability of Data Cache Misses in Nonnumeric Applications
Mowry T., Luk C. IEEE Transactions on Computers 49(4): 369-384, 2000.  Type: Article

The predictability of data cache misses in nonnumeric codes where the compiler is unable to analyze data locality is important, because there is a performance cost to any latency hiding technique. Performance is optimized if these tech...

Jun 1 2001
  An Algorithm for Optimally Exploiting Spatial and Temporal Locality in Upper Memory Levels
Temam O. IEEE Transactions on Computers 48(2): 150-158, 1999.  Type: Article

As caches are ubiquitous in computer system design, understandingthe limits of their performance is of interest. In most situations,optimizing just the traffic (measured in lines or pages moved) is anincomplete optimization, because it...

Aug 1 1999
 
 
 
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