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RISC/CISC, VLIW Architectures (C.1.1...)
Lazy instruction scheduling: keeping performance, reducing power
Mahjur A., Taghizadeh M., Jahangir A. Low power electronics and design (Proceeding of the Thirteenth International Symposium on Low Power Electronics and Design, Bangalore, India, Aug 11-13, 2008) 375-380, 2008. Type: Proceedings
The problem of “useless instruction execution” is addressed in this paper. An instruction is useless if the result is never used. With reasonable compilers, this problem can only take place when conditional branches...
Nov 20 2008
An FPGA-based VLIW processor with custom hardware execution
Jones A., Hoare R., Kusic D., Fazekas J., Foster J. Field-programmable gate arrays (Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field-programmable Gate Arrays, Monterey, California, Feb 20-22, 2005) 107-117, 2005. Type: Proceedings
This is a very exciting piece of research in the general area of configurable, extensible processors and the software/hardware interface. The authors propose a hybrid architecture, consisting of a parameterized very long instruction wo...
May 23 2006
Design of a multimedia processor based on metrics computation
Amor N., Le Moullec Y., Diguet J., Philippe J., Abid M. Advances in Engineering Software 36(7): 448-458, 2005. Type: Article
A novel approach for the creation of a multimedia processor is presented in this paper. Three steps to customize a general-purpose processor (GPP) based on the detailed analysis of a target application are described, and these steps ar...
Jan 5 2006
A cost-effective design for MPEG-2 audio decoder with embedded RISC core
Tsai T., Wu R., Chen L. Journal of VLSI Signal Processing Systems 29(3): 255-265, 2001. Type: Article
The reproduction of MPEG audio files is becoming a hot topic in both the scientific and entertainment arenas, motivating a lot of research in the area with the goal of achieving high performance with contained power consumption. Since ...
Apr 21 2003
Cost-Conscious Strategies to Increase Performance of Numerical Programs on Aggressive VLIW Architectures
López D., Llosa J., Valero M., Ayguadé E. IEEE Transactions on Computers 50(10): 1033-1051, 2001. Type: Article
The authors of this paper have done an excellent job in illustrating the various aspects of looping constructs that affect instruction-level parallelism (ILP) in the course of program execution....
Dec 16 2002
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