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Efficient resource sharing algorithm for physical register file in simultaneous multi-threading processors
Zhang Y., Lin W.  Microprocessors & Microsystems 45, Part B,  270-282, 2016. Type: Article
Date Reviewed: Nov 9 2016

This paper reminds me a lot of previous years of using assembly language and learning to write code with only four registers to hold data. Being trained in these techniques can seriously improve code optimization, as well as how one allocates and manages memory. The paper discusses simultaneous multi-threading (SMT) processors with “concurrent execution of multiple independent threads” sharing data components. The objective of this work is to better utilize resources.

The paper is very well written, discussing complete details of how simulators are used to test the authors’ hypothesis. The authors are able to back up their experiments with validation using analytical tools and comparing how utilization of registers can be improved. According to the paper, “Supporting inter-thread sharing of physical registers, an SMT system processor can reduce ... registers ... required in multiple [actions].”

The authors have recognized that shared resources, such as slower threads, can “lead to inefficient usage of the resources and thus an undesirable performance outcome.” The authors present an algorithm for how these can be efficiently managed, producing a 37 percent improvement in utilization. The paper is particularly useful for control engineering and designing faster processors.

Reviewer:  Mariam Kiran Review #: CR144909 (1702-0129)
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