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	Kim, Taewhan     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending Date Reviewed     1 - 2 of 2 reviews       Leakage power minimization for the synthesis of parallel multiplier circuits Shin K., Kim T.  VLSI (Proceedings of the 14th ACM Great Lakes Symposium on VLSI, Boston, MA, USA, Apr 26-28, 2004) 166-169, 2004.  Type: Proceedings Controlling power leakage is important. This paper presents an optimization approach that uses dual threshold technology, based on experiments using benchmarks. The authors used full adders factored by half adders (FA/HA) in their expe...... Jul 22 2004     Memory allocation and mapping in high-level synthesis: an integrated approach Seo J., Kim T., Panda P. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11(5): 928-938, 2003.  Type: Article The limitations of memory allocation and array mapping to memories are the topics addressed in this paper. As a solution, the authors propose an integrated approach, with a tight link to scheduling effects and a nonuniform access speed...... Feb 4 2004
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