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Dutt, Nikil
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An advanced course design for mobile embedded software through Android programming
Jeong G., Kang D., Lim S., Dutt N. WESE 2012 (Proceedings of the Workshop on Embedded and Cyber-Physical Systems Education, Tampere, Finland, Oct 12, 2012) 1-7, 2013. Type: Proceedings
The students in this study participated in a programming course to learn about an Android development environment with coursework and projects that had a real-world context. The cohort was assessed on weekly lab work and the successful...
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Nov 5 2013
Partitioning techniques for partially protected caches in resource-constrained embedded systems
Lee K., Shrivastava A., Dutt N., Venkatasubramanian N. ACM Transactions on Design Automation of Electronic Systems 15(4): 1-30, 2010. Type: Article
According to this research, a partially protected cache (PPC) architecture is one of the best solutions for reducing the damage of soft errors to embedded processors. A PPC processor contains a protected cache and an unprotected one. T...
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May 5 2011
On-chip communication architectures: system on chip interconnect
Pasricha S., Dutt N., Morgan Kaufmann Publishers Inc., San Francisco, CA, 2008. 536 pp. Type: Book (9780123738929)
Over the past decades, on-chip integration has been one of the major forces behind the performance improvements in electronic and computing systems. First, memory and application-specific accelerators made their way into processor chip...
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May 6 2009
Compiler driven data layout optimization for regular/irregular array access patterns
Cho D., Pasricha S., Issenin I., Dutt N., Paek Y., Ko S. ACM SIGPLAN Notices 43(7): 41-50, 2008. Type: Article
Memory access patterns on multiprocessor systems-on-chip (MPSoC) are complex enough that they often defeat hardwired caching strategies. Instead of hardwired caches, these systems use scratch pad memory (SPM), acting as a software-cont...
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Aug 15 2008
Modeling and validation of pipeline specifications
Mishra P., Dutt N. ACM Transactions on Embedded Computing Systems 3(1): 114-139, 2004. Type: Article
This paper presents a verification and validation (V and V) approach for processor, memory, and coprocessor pipelines, described in an architecture description language (ADL). The V and V approach uses a graph-based model of the archit...
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Jun 11 2004
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