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  Roy, Kaushik Add to Alert Profile  
 
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  Efficient testing of SRAM with optimized March sequences and a novel DFT technique for emerging failures due to process variations
Chen Q., Mahmoodi H., Bhunia S., Roy K. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13(11): 1286-1295, 2005.  Type: Article

Anyone interested in very large-scale integration (VLSI) circuit design, the effects of manufacturing process parameter variations, failure mechanisms in VLSI chips, fault modeling of chip failures, testing VLSI chips, design for test ...
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Oct 13 2006  
  A novel wavelet transform-based transient current analysis for fault detection and localization
Bhunia S., Roy K. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 13(4): 503-507, 2005.  Type: Article

In this interesting paper, Bhunia and Roy present a novel integrated method for fault detection and localization, using wavelet transform-based IDD waveform analysis. The authors demonstrate that the wavelet transform has better sensit...
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Nov 29 2005  

   
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