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	Sharkey, Joseph J.     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending Date Reviewed     1 - 3 of 3 reviews       Reducing register pressure in SMT processors through L2-miss-driven early register release Sharkey J., Loew J., Ponomarev D. ACM Transactions on Architecture and Code Optimization 5(3): 1-28, 2008.  Type: Article Superscalar processors and register renaming make it easy to simulate multiple processors on a single physical processor, improving the utilization of the computing units. When a memory reference to a location that is no...... Feb 27 2009     Exploiting operand availability for efficient simultaneous multithreading Sharkey J., Ponomarev D. IEEE Transactions on Computers 56(2): 208-223, 2007.  Type: Article Sharkey and Ponomarev seek to reduce scheduling complexity in instruction queues (IQs), and to make better use of the instruction queue for dispatching instructions. Specifically, the paper discusses the dynamic scheduling of instructi...... Jul 12 2007     Instruction packing: reducing power and delay of the dynamic scheduling logic Sharkey J., Ponomarev D., Ghose K., Ergin O.  Low power electronics and design (Proceedings of the 2005 International Symposium on Low Power Electronics and Design, San Diego, CA, Aug 8-10, 2005) 30-35, 2005.  Type: Proceedings A new technique, instruction packing, is proposed in this paper, for use in the microarchitectures of superscalar processors. Traditionally, instructions are scheduled dynamically, using instruction queues (IQs). In instruction packing...... Oct 21 2005
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