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	Weiser, Uri C.     Options: All Media Types Journals Proceedings Div Books Whole Books Other Date Reviewed Title Author Publisher Published Date Descending Ascending Date Reviewed     1 - 1 of 1 reviews        Utilizing shared data in chip multiprocessors with the Nahalal architecture Guz Z., Keidar I., Kolodny A., Weiser U.  SPAA 2008 (Proceedings of the 20th Annual Symposium on Parallelism in Algorithms and Architectures, Munich, Germany, Jun 14-16, 2008) 1-10, 2008.  Type: Proceedings In a multicore processor chip, the L2 cache may be organized as one private L2 cache per core or a single shared L2 cache. The private cache approach requires smaller caches than a shared cache, and thus has faster cache access time th...... Dec 23 2008
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