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Kantabutra, Vitit
Idaho State University
Pocatello, Idaho
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  Low-Power Divider
Nannarelli A., Lang T. IEEE Transactions on Computers 48(1): 2-14, 1999.  Type: Article

This paper presents a multi-method approach to low-power design.The authors have chosen a good problem (division) to work on. It is agood choice because in such a complex problem, it is possible tominimize energy consumption at many le...

Jul 1 1999  
  Fundamentals of modern VLSI devices
Taur Y., Ning T., Cambridge University Press, New York, NY, 1998.  Type: Book (9780521559591)

This well-written classroom text on VLSI devices is intended for advanced undergraduates and graduate students. Though written as a classroom text, complete with exercises, this book will also prove valuable to practicing designers and...

May 1 1999  
  Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations
Nekili M., Bois G., Savaria Y. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 5(2): 161-174, 1997.  Type: Article

A novel solution to the problem of clocking large, high-speed digital systems is presented in this paper. The authors suggest a new deterministic mathematical model for clock skew, modifying a known method for clocking large digital sy...

Feb 1 1998  
  An optimal clock period selection method based on slack minimization criteria
Chang E., Gajski D., Narayan S. ACM Transactions on Design Automation of Electronic Systems 1(3): 352-370, 1996.  Type: Article

In an automatic digital circuit synthesis system, the clock period is either specified by the designer or determined automatically by the synthesis system. The former situation occurs, for example, when the system under synthesis is pa...

Sep 1 1997  
  Design and realization of high-performance wave-pipelined 8 × 8 b multiplier in CMOS technology
Ghosh D., Nandy S. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 3(1): 36-48, 1995.  Type: Article

A wave-pipelined 8-bit multiplier is presented. Its novelty lies in the use of a nonstatic variant of CMOS technology, NPCPL. The advantage of NPCPL over other technologies suitable for wave-pipelining, such as ECL and CML, is that it ...

Nov 1 1996  
  Digital circuit design for computer science students
Wirth N., Springer-Verlag, London, UK, 1995.  Type: Book (9783540585770)

When high-level programming languages sorely needed simplification and clarification in the 1960s and 1970s, Niklaus Wirth came to the rescue with Algol W and Pascal, which evolved into Modula and Oberon. Now hardware description langu...

Sep 1 1996  
  Numerical programming the 386, 486, and Pentium
Sanchez J., Canton M., McGraw-Hill, Inc., New York, NY, 1995.  Type: Book (9780079118325)

The authors discuss programming the Intel floating point units (FPUs) in assembly language from a programmer’s point of view. That is, the book does not include details about how the floating point units perform the arithmeti...

Feb 1 1996  
  Hardware Implementation of Montgomery’s Modular Multiplication Algorithm
Eldridge S., Walter C. IEEE Transactions on Computers 42(6): 693-699, 1993.  Type: Article

Hardware that quickly computes A × B mod M is described. The basic algorithm that this hardware uses for such computation is the one presented first by P. L. Montgomery [1] and further de...

Oct 1 1994  
  Delay Optimization of Carry-Skip Adders and Block Carry-Lookahead Adders Using Multidimensional Dynamic Programming
Chan P., Schlag M., Thomborson C., Oklobdzija V. IEEE Transactions on Computers 41(8): 920-930, 1992.  Type: Article

The speed of carry-skip adders and block carry-lookahead adders depends on how bit positions are grouped together into blocks (that is, how many bits are in a block) and on how these blocks are further grouped together. Unequal block ...

Jul 1 1993  
  Four State Asynchronous Architectures
McAuley A. IEEE Transactions on Computers 41(2): 129-142, 1992.  Type: Article

Wave-front arrays are the asynchronous counterparts to the popular systolic arrays. The design principle for wave-front arrays presented in this paper is based on the encoding of the two possible data bit values with four different st...

Mar 1 1993  
 
 
 
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