A novel solution to the problem of clocking large, high-speed digital systems is presented in this paper. The authors suggest a new deterministic mathematical model for clock skew, modifying a known method for clocking large digital systems. The known method is to use a set of interconnected metallic lines organized as a symmetrical tree, called an  H-tree,  in which the interconnections that carry the signals toward the subblocks of the circuit are of equal length. The conventional H-tree clocking method is limited by the bandwidth of the clock network, especially when the network is large. Therefore, the authors modify this method by using an H-tree whose branches consist of abutted minimum-sized inverters instead of metallic lines. All leaves of the H-tree are equidistant from the root (meaning that the number of inverters between a leaf and the root is the same for each leaf). Therefore, theoretically at least, there appears to be little clock skew. Each leaf may be many periods out of phase with the root where the clock signal originates, but all of the leaves are, theoretically, in phase with each other.

The results are theoretically interesting, but there are questions regarding their applicability. For example, the path from the root to each leaf may involve many clock periods, so a small error in the mathematical model may accumulate and result in significant clock skew. Also, the authors do not present a convincing argument that the heat generated by all of the inverters, along with that generated by the rest of the circuit, can be dissipated effectively.