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ACM Transactions on Design Automation of Electronic Systems
1-10 of 61 reviews
Optimization and quality estimation of circuit design via random region covering method
Bi Z., Zhou D., Wang S., Zeng X. ACM Transactions on Design Automation of Electronic Systems 23(1): 1-25, 2017. Type: Article
Bi et al. propose a random region covering theory to optimize designs on systems and circuits. The proposed work has been verified on a class-E power amplifier and a cascade local impedance attenuation amplifier. Both are analog circuits with a si...
Jan 26 2018
Genetic-algorithm-based FPGA architectural exploration using analytical models
Mehri H., Alizadeh B. ACM Transactions on Design Automation of Electronic Systems 22(1): 1-17, 2016. Type: Article
Mehri and Alizadeh use the genetic algorithm (GA) to optimize field-programmable gate array (FPGA) architectural performance involving area, delay, and power consumption. Compared with the traditional geometric programming (GP) algorithm that requ...
Nov 9 2016
Improving write performance by controlling target resistance distributions in MLC PRAM
Kim Y., Yoo S., Lee S. ACM Transactions on Design Automation of Electronic Systems 21(2): 1-27, 2016. Type: Article
Memory technology is important to everyone who wants his computer to be faster. Dynamic random-access memory (DRAM) has been used as the main memory technology for decades, but it has some overhead related to its cost and power consumption. Resear...
Apr 19 2016
Dynamic power management for multidomain system-on-chip platforms: an optimal control approach
Bogdan P., Marculescu R., Jain S. ACM Transactions on Design Automation of Electronic Systems 18(4): 1-20, 2013. Type: Article
Power management for increasingly complex microprocessor systems-on-chips (MPSoCs) is a significant challenge. Existing linear control models are ineffective where communications are via a network-on-chip (NoC), and these controls cannot adequatel...
Jan 13 2014
An ILP solution to address code generation for embedded applications on digital signal processors
Salamy H., Ramanujam J. ACM Transactions on Design Automation of Electronic Systems 17(3): 1-23, 2012. Type: Article
Digital signal processors (DSPs) often have very strict limitations on their cord size and power consumption. Many of them do not support base-plus-offset addressing mode to simplify their architecture implementations. In many of these irregular a...
Jul 10 2013
Hybrid nonvolatile disk cache for energy-efficient and high-performance systems
Shi L., Li J., Jason Xue C., Zhou X. ACM Transactions on Design Automation of Electronic Systems 18(1): 1-23, 2012. Type: Article
This paper presents the construction of a hybrid cache for magnetic disks built from a combination of phase change memory (PCM) and more traditional flash memory. Unlike traditional flash memory, PCM is byte addressable, enables in-place updates a...
Jun 14 2013
A self-tuning design methodology for power-efficient multi-core systems
Sun J., Zheng R., Velamala J., Cao Y., Lysecky R., Shankar K., Roveda J. ACM Transactions on Design Automation of Electronic Systems 18(1): 1-24, 2012. Type: Article
Higher voltages improve transistor switching times, but the speed achievable at a fixed voltage degrades with use. That degradation is also temperature specific. This means that a new multicore central processing unit (CPU) will have to either run...
May 2 2013
Using implications to choose tests through suspect fault identification
Dworak J., Nepal K., Alves N., Shi Y., Imbriglia N., Bahar R. ACM Transactions on Design Automation of Electronic Systems 18(1): 1-19, 2012. Type: Article
Building upon previous work that used login implications to improve the reliability of digital circuits in detecting online faults, this paper adds diagnosis properties to help localize the portion of the circuit where the fault has occurred....
Apr 25 2013
Dimension-reducible Boolean functions based on affine spaces
Bernasconi A., Ciriani V. ACM Transactions on Design Automation of Electronic Systems 16(2): 1-21, 2011. Type: Article
We typically synthesize combinational Boolean logic functions into structures based on two-level or multi-level implementations. For complex logic functions, a two-level implementation has less delay but takes a larger silicon area than a multi-le...
Jun 30 2011
Partitioning techniques for partially protected caches in resource-constrained embedded systems
Lee K., Shrivastava A., Dutt N., Venkatasubramanian N. ACM Transactions on Design Automation of Electronic Systems 15(4): 1-30, 2010. Type: Article
According to this research, a partially protected cache (PPC) architecture is one of the best solutions for reducing the damage of soft errors to embedded processors. A PPC processor contains a protected cache and an unprotected one. Therefore, wh...
May 5 2011
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