This short (about 1000 words) paper presents an overview of SYSIM, a simulator for systolic arrays. This tool is supposed to supplement the existing spectrum of lower-level (switch-level and electrical) simulation facilities by providing a hardware simulation vehicle that operates on the intercell communication and synchronization level. The first section of the paper outlines the major features of the tool, which supports hierarchical definition of cells and has both interactive and off-line simulation modes.
The second section describes the simulation language constructs, which can be divided into three main groups:
(1)commands for defining cells, arrays, clocks, connections, streams of data, and functions (including user-defined ones);
(2)commands for manipulating programs with these definitions (by creating, editing, loading, saving, listing, and running them); and
(3)commands for organizing the simulation process (setting cyclic and stepwise modes, tracing the contents of registers, etc.).
This section also includes a set of appropriate data types and corresponding operators. The third section depicts the implementation issues via a brief description of a simulation procedure. The procedure is characterized as a recursive process, where the level of recursion depends on the hierarchical capacity of the systolic array.
In the fourth section, the author summarizes the paper and reports on experiments that used SYSIM for various systolic algorithms. He also emphasizes the possibility of using the tool for purposes such as top-down design.
I have a few complaints, however. The author uses terms, such as “wild cards,” which may look odd to an inexperienced reader. He also says “no recursive functions are allowed because of the difficulty in hardware realization,” which is a bit confusing since the primary purpose of the tool is to simulate, not to realize, hardware. Also, the paper contains a lot of misleading typos for how short it is: “may” appears instead of “many”, “connectness” instead of “correctness.”
Nevertheless, the paper is interesting and will obviously find a large audience consisting primarily of VLSI design engineers. It would also be instructive for students working or starting to work on software tool design projects.
