The motivation and design of three simulators built to support the development of the Motorola PowerPC 603 and 604 microprocessors are discussed. Two of these simulators are standalone simulators: one is designed to provide architectural emulation for the purposes of software development, and the other is designed as a timing simulator for hardware modeling and performance evaluation. In the words of the paper, the first simulator has to run “PowerPC code as accurately and as quickly as possible,” while the second “accurately models both the instruction set semantics and the detailed pipeline behavior of a PowerPC microprocessor implementation.” The third simulator is an embedded simulator.

The paper has four main parts. The first section identifies some of the software engineering issues in the design of the simulators themselves. It is followed by three sections, each of which describes facets peculiar to one of the simulators. Throughout the paper, I was never sure whether the intent was to describe the simulation issues or the software engineering issues, as the two themes seem to be intertwined.

Although this paper appears in a special issue dedicated to the PowerPC, it contains little that directly relates to that architecture. I found it interesting insofar as it gives some insight into the design of the simulators, but there is little deep technical insight. The author focuses more on the use of C++ to facilitate the simulator design than on the architectural features and how they relate to the issues of software tool support identified in the blurb. In the conclusion, the author lists several innovative features of the family. All of these relate more to software engineering than to the PowerPC.