The stated purpose of this book is to integrate hardware description languages into the digital design process at all levels of abstraction. In particular, the authors seek to integrate VHDL into the design process, starting with a high-level model that provides an executable version of the specification and concluding with a gate-level implementation in the form of ASICs or FPGAs. They have succeeded in this goal.

Chapter 1 is an introduction to the structured design concepts and abstraction hierarchy. It introduces pictorial and textual representations. Chapter 2 provides the CAD tool taxonomy and introduces design tools such as schematic editors, simulators, and synthesis tools.

Chapter 3 is a complete introduction to VHDL. Numerous code blocks are woven into the description of various aspects of VHDL, making the chapter easy to read and understand.

Chapter 4 deals with VHDL modeling techniques, including delay modeling, concurrency, scheduling algorithms, modeling combinational and sequential logic primitives, and testing models.

Chapter 5 details algorithm-level design through the description of process model graphs, timing issues, and system interconnection representation. Multivalued logic, multiplexing, and intermodule communication aspects of algorithmic modeling are covered.

Chapter 6 describes register-level design and introduces dataflow concepts, timing analysis, and control unit design. It details the design of the control unit of a RISC machine.

Chapter 7 introduces gate-level and ASIC modeling. The authors explain gate modeling with a variety of timing and delay models, back annotation concepts, and the IEEE’s  VITAL.  There are sections on error checking, multivalued logic models, configuration declarations, race/hazard modeling, and delay control approaches.

Chapter 8 integrates the use of hardware description languages with Karnaugh maps and state tables for logic design. Detailed design techniques for combinational and sequential logic circuits and microprogrammed control units are provided.

Chapter 9 introduces ASIC- and FPGA-based designs. It covers ASIC and FPGA primitive concepts; the use of Synopsis tools to synthesize ASICs using the standard cell library; and the implementation of ASICs using Xilinx FPGA design tools.

Chapter 10 is devoted to modeling techniques for hardware synthesis. Various behavior models and their use, simulation/synthesis semantics, modeling sequential behavior, modeling combinational circuits for synthesis, latches and don’t cares, tristates, and resource sharing concepts are detailed.

Chapter 11 integrates VHDL into the top-down design methodology. Requirements gathering, architecture development, and detailed design concepts are illustrated by numerous examples and tool scenarios.

Chapter 12 concludes the book with a discussion of synthesis algorithms for design automation. It provides details on algorithmic synthesis tasks, scheduling techniques, allocation techniques, and the automated synthesis of VHDL constructs.

Each chapter ends with a very good set of problems of varying complexity. The examples and VHDL segments are well thought out. The description of commercially available tools is adequate.

The book is a good contribution to this field. It is suitable for use as a textbook and can be used as a reference by professional logic designers.