This paper reports a new synchronization algorithm for simulation of mixed-signal (analog and digital) circuits with the language VHDL-AMS.

VHDL is a standardized language for hardware description, useful for simulation and development of digital circuits. Recently, the IEEE has released a new standard that adds to the language new statements, structures, declarations, and data types to deal with analog and mixed signals. The extended language is called VHDL-AMS, and the standard is the IEEE 1076.1-1999.

A very clear and synthetic introduction to VHDL-AMS and to the extensions added are presented. Readers must be familiar with VHDL, however.

After the introduction, the simulation environment is described, by reporting the simulation cycle in the case of mixed-signal simulation. A new synchronization algorithm is proposed. Unlike the canonical algorithm, this algorithm allows the setting of an analog solution point beyond the expected point of synchronization with the digital part of the signal. As a consequence, the synchronization between the analog solver and the digital simulation is more flexible. Backtracking is necessary if a discontinuity is flagged by using a break statement. (This is new in this language.)

For case studies, the authors propose two typical mixed-signal circuits, an analog-to-digital converter and a phase locked loop (PLL) model. The two circuits are described with a behavioral model in VHDL-AMS, and simulated with both canonical and newly presented synchronization algorithms. The reported results demonstrate that the new algorithm is more efficient in terms of execution and simulation time than the canonical algorithm, in particular when there are many digital events.