At just over 100 pages, this book can be read in a few hours, and will serve as a reference for years. While it is not essential reading, it could serve as a reference on an as-needed basis. Reading it actually enables readers to understand how to use it as a reference in the future.

Forty-five modifications in the Verilog hardware description language (HDL) are presented, ranging from minor to major. The author has done a nice job of removing the dryness of the standard text, and presenting the reader with an easy to memorize template for describing the features, namely: background, or what I would term existing state of affairs in the current standard; what is new or demonstrates how the feature has been enhanced or modified; and synthesis considerations, which demonstrates the amenability to synthesis in hardware of the particular feature. Sometimes this last section is redundant, for example, nobody would ever assume system tasks can be synthesized.

When relevant, there is a section on backwards compatibility issues, and a box with notes pertaining to items not in the main text, such as non-completed items, which were not in the book when it was written, with some pointers that tell readers where to look for them. What makes the book ideal for reference is that most topics are contained in two or three pages; exceptions are made for the very important enhancement on generate blocks with twice this number of pages, and some others like enhanced file Input/Output (I/O), configurations, and so on. The last topic considered is about the enhanced programming language interface (PLI) support, but the reader should turn to another book by the same author, The Verilog PLI handbook: a users guide and comprehensive reference on the Verilog programming language interface [1]. There are a few erroneous statements, which are minor and can be relegated to the status of minor typos. Overall, this is a timely and very well-designed reference to new features and modifications of the Verilog 2001 HDL standard.