The authors explore how to use nanowires (NWs) to build sublithographic programmable logic arrays (PLA).

The paper describes the construction of a two-plane PLA, with decorated silicon NWs. These NWs served as the primary interconnect and device building blocks, which are discussed in section 2. These concepts are illustrated by a number of understandable figures. Section 3 demonstrates how to achieve restoring logic, and a precharge clocking scheme for logic evaluation is shown in section 4. In section 5, this concept is extended, and in section 6, the area, timing, and yield of these devices is calculated using a set of formulas, which are provided. In section 7, the discovery of the basic state of the devices, to enable configuration and defect avoidance, is sketched out. In section 8, several data paths are benchmarked.

The new contributions in this work include the explicit formulation of NW-based PLAs, with separate programmable and restoring devices; the introduction of stochastic techniques for building fixed restoring logic; the introduction of a PLA topology that requires lithographic programming lines in only one dimension, and allows programming to be shared across multiple arrays; the introduction of a clocked precharged scheme for sub lithographic PLA logic; the introduction of simple topologies for physically configuring PLA cycles; and the estimation of net logic density, using mapped logic instances from both standard programmable logic benchmarks, and focused data path elements. This is a formidable set of contributions, and the paper deserves a careful read. The material is quite technical, however, and without a background in engineering, computer science, physics, or mathematics, it will be difficult to follow.