Timing closure is an important step in the design of digital systems. With the advent of deep submicron complementary metal-oxide semiconductor (CMOS) technology, and the increasing complexity of digital systems, it is critical to obtain timing closure in the first pass of the design. Sapatnekar reviews important topics related to timing in integrated circuits, in an organized manner.

Circuit simulation provides an accurate estimate of timing information; it is, however, too slow to use in digital circuits. In chapter 2, an overview of circuit simulation techniques is presented.

In chapter 3, reduced-order models of circuits, for getting a quick estimate of timing information, are presented. The Elmore delay metric, a first-order expression for delay, is discussed. Following this, a number of higher order models that trade accuracy for computational time are presented, such as asymptotic waveform evaluation (AWE), passive reduced-order interconnect macromodeling algorithm (PRIMA), and time constant equilibration reduction (TICER). Some examples are provided to illustrate the application of these models. Timing analysis of the combinational logic stage is presented in chapter 4. Methods of calculating effective capacitance when the interconnect net is modeled using capacitive, resistive-capacitive, and resistive-inductive-capacitive elements are reviewed. Capacitive coupling effects are becoming significant in modern digital circuits. The timing window computations that account for coupling capacitance effects on the signal delays are reviewed. Combinational logic systems are made up of a number of combinational stages that are connected. The delay computation of the combinational logic system is presented in chapter 6. Procedures to calculate delay in a critical path of a combinational circuit are reviewed. The effect of false paths on timing analysis is also analyzed.

There is significant variation of process parameters in intra-die and inter-die circuitry in very deep submicron devices. An introduction to a statistical model of gate delay probability density function (PDF) is presented in chapter 7, along with an overview of approaches that use statistical static timing analysis with spatial correlation.

In chapter 8, sequential timing analysis is presented. After an introduction to clocking techniques used in sequential circuits, constraints for timing verification are presented. Techniques for clock schedule optimization to determine minimum clock period are presented. Finally, techniques for timing analysis for domino logic, a high-speed dynamic logic, are summarized.

Timing analysis is the most important issue in clock distribution and clock skew reduction within synchronous systems. Chapter 9 covers important timing-related concepts, such as clock distribution networks, zero skew clock distribution, clock skew optimization, retiming issues, and wave pipelining. Techniques that use deliberate clock skew to reduce switching noise in synchronous systems are reviewed.

Retiming is a technique used to optimize sequential circuit timing, where part of a clock cycle is borrowed or shared between synchronous elements. Chapter 10 reviews several algorithms used to optimize clock period, and areas for edge-triggered and latch-based circuits.

In summary, the book provides a very good introduction to a number of relevant topics in timing analysis and optimization. A rich collection of references is provided. The target audience is researchers working in the area of circuit and timing simulation, and computer-aided design (CAD) tool developers. Although the presentation of material is useful for graduate students working in the fields of high-speed electronic systems design and design automation, the book lacks the exercises that would be needed for it to be used as a textbook. I would recommend this book as a very good and timely reference to the field of timing analysis.