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Understanding the energy efficiency of simultaneous multithreading
Li Y., Brooks D., Hu Z., Skadron K., Bose P.  Low power electronics and design (Proceeding of the 2004 Iinternational Symposium on Low Power Electronics and Design, Newport Beach, California, USA, Aug 9-11, 2004)44-49.2004.Type:Proceedings
Date Reviewed: Nov 23 2005

Power consumption has become a major concern in microprocessor design. This paper presents a detailed study of the relative power-performance efficiency of simultaneous multithreading (SMT), a new microarchitectural paradigm, using a power-performance modeling toolkit called PowerTimer.

There are two main factors for the power uplift of SMT compared with single-threaded microarchitectures: one is due to resource scale, and another is due to resource utilization. The modeling results indicate that “SMT is a very power-efficient design paradigm in terms of ED2 and can provide a 20 percent performance improvement for a varied mix of workloads with a power overhead of around 24 percent.”

This is a good paper for learning about SMT power consumption. One concern is that only the average results of the power consumption from all workloads are presented; it would be better to show more results for each individual workload, since the effect may change significantly from one workload to another. The authors should also provide more evidence to support their confidence in, and the accuracy of, their results.

Reviewer:  Hongzhang Shan Review #: CR132075 (0610-1049)
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Processor Architectures (C.1 )
 
 
General (B.0 )
 
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