Field-programmable gate arrays (FPGAs) are ideal platforms for prototyping hardware, due to the fast turnaround time and inherent reconfigurable nature of the devices. FPGAs are increasingly being used in low-to-medium-volume markets. Although their performance is superior to software implementations, FPGA implementations still have significantly lower speeds than application-specific integrated circuit implementations. To reduce this performance gap, FPGAs are equipped with additional hardware and programmable features to improve the performance of arithmetic blocks.

Compressor trees are very suitable for multiple digit addition and fast multiplication applications. The authors present new enhancements to commercial FPGA architectures that make it easier to implement 6:2 and 7:2 compressors. The paper has a good introduction to arithmetic primitives and their mapping onto the FPGA hardware resources. The authors describe the cell modifications to improve the performance of arithmetic primitives. They discuss in detail the heuristics to map compressor trees to the modified FPGA cells. They study the critical path delay, power consumption, and four different implementations of multiple benchmark arithmetic circuits, on the modified FPGA architecture. The four implementations are ternary, generalized parallel counters (GPC), GPC with 6:2 compressors, and GPC with 7:2 compressors.

Overall, the implementations based on compressors have significantly reduced delays, with an increase in the use of FPGA resources and power consumption. The paper should be of interest to researchers in the areas of FPGA architectures and computer arithmetic.