Soliman and Abozaid present the performance evaluation of FastCrypto, an encryption and decryption crypto coprocessor. The authors describe the implementation of the advanced encryption standard (AES), which is commonly used in various cryptography applications. The AES algorithm is very computationally intensive and has been implemented on different platforms including graphics processing units (GPUs), application-specific integrated circuits (ASICs), and field-programmable gate arrays (FPGAs).

FastCrypto, the authors’ AES crypto coprocessor, supports both encryption and decryption. The FastCrypto core is implemented using the VHSIC hardware description language (VHDL) on a Xilinx Virtex-5 FPGA, resulting in lower power dissipation. The authors evaluate the performance of the FastCrypto core with respect to the following design parameters: the number of parallel AES pipelines, the load and store data queue effect, the load and store address queue, and the effect on memory latency when the bus width and memory ports are increased.

The authors compare FastCrypto’s performance with existing cryptography implementations and conclude that FastCrypto achieves maximum throughput and maximum performance.