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1 - 8 of 8
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 Memory system design space exploration for low-power, real-time speech recognition
Krishna R., Mahlke S., Austin T. Hardware/software codesign and system synthesis (Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, Stockholm, Sweden, Sep 8-10, 2004) 140-145, 2004. Type: Proceedings
As its title explains, this paper investigates memory systems, and suggests a memory hierarchy for a specific application. The application is speech recognition, and the architecture recommended is a combination of an XScale processor ...
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Dec 2 2004 |
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A self-tuning cache architecture for embedded systems
Zhang C., Vahid F., Lysecky R. ACM Transactions on Embedded Computing Systems 3(2): 407-425, 2004. Type: Article
Tunable cache organization, particularly for embedded systems, is discussed in this paper. Its motivation is that 60 percent of the energy in embedded systems is spent in cache. To reduce such energy consumption--currently one...
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Aug 10 2004 |
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An energy efficient cache memory architecture for embedded systems
Jung-Wook P., Cheong-Ghil K., Jung-Hoon L., Shin-Dug K. Applied computing (Proceedings of the 2004 ACM symposium, Nicosia, Cyprus, Mar 14-17, 2004) 884-890, 2004. Type: Proceedings
This paper presents a version of skewed associative cache, called selective-way-access skewed associative (SSA), for embedded systems. The SSA illustrates less energy consumption in comparison with direct mapped and two-way/four-way se...
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May 21 2004 |
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Low-leakage asymmetric-cell SRAM
Azizi N., Najm F., Moshovos A. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 11(4): 701-715, 2003. Type: Article
This work introduces a new cache (static random access memory (SRAM)) memory cell, composed of asymmetric transistors, and intended to reduce leakage current, and, consequently, power dissipation....
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Mar 10 2004 |
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An analysis of operating system behavior on a simultaneous multithreaded architecture
Redstone J., Eggers S., Levy H. Architectural support for programming languages and operating systems (Ninth international conference, Cambridge, Massachusetts, United States, Nov 12-15, 2000) 245-256, 2000. Type: Proceedings
An attempt to address operating system workload performance on simultaneous multithreaded (SMT) architecture is presented in this paper. The authors used an eight-thread SMT simulator for their analysis (the hardware parameters are pro...
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Sep 25 2003 |
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GENESIS: an efficient, transparent and easy to use cluster operating system
Goscinski A., Hobbs M., Silcock J. Parallel Computing 28(4): 557-606, 2002. Type: Article
You may not like the way that this paper is written, but as you follow through it, you will like it more and more. This is a very thorough work on parallel processing, specifically about the parallel programming paradigm....
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Jun 19 2003 |
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Design and implementation of a parallel I/O runtime system for irregular applications
No J., Park S., Perez J., Choudhary A. Journal of Parallel and Distributed Computing 62(2): 193-220, 2002. Type: Article
In a group of scientific and engineering applications (teraflop applications included), data should be rearranged into a canonical form for processing. An example of structural practice in such applications is indirection arrays that f...
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Apr 23 2003 |
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HiPER: A Compact Narrow Channel Router with Hop-by-Hop Error Correction
May P., Bunchua S., Wills D. IEEE Transactions on Parallel and Distributed Systems 13(5): 485-498, 2002. Type: Article
The paper presents the so-called high-performance efficient router (HiPER), a smart design that combines mad-postman switching with dimension order routing. ...
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Feb 5 2003 |
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