Tunable cache organization, particularly for embedded systems, is discussed in this paper. Its motivation is that 60 percent of the energy in embedded systems is spent in cache. To reduce such energy consumption--currently one of the main trends in embedded systems research--the paper presents a self-tunable cache that results in a better cache miss rate based on the type of application. “Lower cache miss rate” is synonymous with “less energy consumed,” since fewer off-chip accesses are needed.

The authors use a reconfigurable cache organization, with three changeable parameters: cache size, associativity, and block size. Way prediction is also supported in their design. They have designed a finite state machine (FSM) that heuristically finds the best configuration for the running application. Based on the FSM result, the cache can be tuned to perform the best in terms of energy consumption. The empirical simulated results show that this approach saves 40 percent of total memory access energy, in comparison with conventional cache.

The paper is well written, with a lot of information for readers. The authors state reasonable energy equations, which can be used for further design along the same lines. On average, a good reduction in the energy consumed in the memory system is reported. The authors, however, have not shown the degradation in execution performance as a result of their approach; in fact, they have not shown any execution time data. SimpleScalar tool set, which they used in their experiments, is fully equipped to report cycle execution time, and the authors failed to include such data in their paper. There are techniques that could simply report better cache behavior; I wonder how much benefit this paper’s idea would reveal on top of, for example, stream buffers, which are very well behaved in multimedia applications.