Rather than investigating the effects of different cache parameters, this simulation study on instruction memory traffic in the presence of a cache focuses on processor design issues. As pointed out by the authors, this paper “represents the first broad study of the effects of processor architectures on cache performance.”

The paper considers three families of processor architectures--stack architectures, register set architectures, and direct correspondence architectures (architectures featuring a high degree of correspondence to the high-level language). All the architectures share the same ALU vocabulary, but they exhibit significant differences in instruction formats and instruction encoding density.

The authors restrict the analysis to those aspects of cache architecture that are known to have primary effects on performance, that is, the cache size, the line size, and the degree of associativity. They concentrated on 24 different cache configurations by selecting six cache sizes from 512 to 16,384 bytes, lines of size 8 and 16 bytes, and associativities of degree 1 and 2.

The benchmark programs were written in Pascal. They are representative of medium-size high-level-language programs for workstation applications. The static benchmark sizes for stack architecture range from 8,948 to 73,980 bytes, and the dynamic sizes from 2,538,512 to 35,113,324 bytes.

The paper points out the cache design factors that should be taken into consideration in making processor architecture choices. It suggests several interesting space-time tradeoffs between processor architecture and cache architecture, with special reference to microprocessor implementations.

The paper is carefully motivated and well organized, and can be read with reasonable effort by the specialist in the field. The presentation clearly identifies the most important results and their architectural implications.

From a methodological point of view, the paper represents an important effort in organizing a variety of measurement and simulation results concerning a wide spectrum of processor and cache architectures into a unitary framework. It will definitely be useful reading for the computer architect involved in the design of a novel architecture or in the implementation of an existing architecture with memory caching features. As far as classroom utilization is concerned, the paper can profitably be used in case study analysis of processor and memory design.