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Designing multibus priority resolver by means of a field programmable logic sequencer
Constantinescu C. Microprocessing and Microprogramming13 (5):325-330,1984.Type:Article
Date Reviewed: Nov 1 1985

This paper presents a design of a bus priority resolver for Multibus using a Programmable Logic Array (PLA). It contains all the necessary technical information required to duplicate the design. The material is clear and well presented. However, this paper is not an exhaustive examination of priority resolution schemes, nor is it a compelling argument that the presented implementation is the definite solution.

Reviewer:  P. C. Yew Review #: CR109119
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Interconnection Architectures (C.1.2 ... )
 
 
Miscellaneous (B.6.m )
 
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