This paper presents the results of a large number of measurements on the performance of MIPS, a 32-bit reduced instruction set computer (RISC) architecture implemented at Stanford University between 1981 and 1984 as a single-chip microprocessor. Special features of this architecture are word addressing, multiple-operation instructions, and pipelining. The measurements were performed by executing a set of benchmark programs, written in Pascal and C, whose lengths ranged from 32 to 14,311 lines of source code (the static and dynamic characteristics of each program are carefully reported). The paper pays special attention not only to the salient features of the instruction set performance (e.g., operation code distribution and addressing mode utilization), but also to such important aspects of the internal organization of the architecture as the use of machine resources and the efficiency of the pipeline. An attempt is made to compare some of these results with data available in the literature for the VAX architecture. Unfortunately, this issue is addressed only marginally.

The paper gives a brief but adequate description of the MIPS architecture. The references include introductory works on the RISC concept as well as several papers, written by the members of the MIPS project team, in which the reader can find the rationale for the MIPS design. An in-depth examination of the architectural implications of each measurement is also provided. As the authors carefully point out, measurements depend on the benchmark programs as well as on the machine-compiler complex. In spite of this fact, this self-contained and well-structured paper is definitely useful reading for every computer architect involved in instruction set design.