The authors give an exceedingly brief overview of the PIPE processor, describe a single-chip nMOS implementation, and discuss some of the implications of the implementation experience for the design of the processor. The chief novelty of the processor design is the use of queues to handle the interface to memory. This allows split-phase memory access, visible to the programmer or compiler, so that the processor clock speed need not be coupled to the memory speed.

The main fault of the paper is that the processor design is not described in sufficient detail to allow us to understand the conclusions drawn from the implementation experience. Also, the processor design seems, from the references, to be more than five years old, and the implementation uses very modest technology. Thus the applicability of the conclusions seems limited.